8086 Features & Architecture

Features of 8086 Microprocessor:

i)  It is a 16 bit processor, contains approximately 29,000 transistors & fabricated using HMOS technology.

ii)  The number of address lines are 20, so addressing capability of this is 2²⁰ = 1 MB.

iii)It has 20 address lines in which 16 lines are multiplexed with data lines.

iv) There are 16 control lines for providing the handshaking signals during bus transfer & for permitting at least some control to CPU.

v)  It requires only +5v DC supply.

vi)Its operating frequency is above 5 MHz (8086-1 requires operating frequency of 10 MHz & 8086-2 requires operating frequency of 8 MHz)

vii) In 40 pin configuration it has provided with two ground pins, pin no 1 & pin no 20.

viii) Input output current levels yield 350mV noise immunity for logic 0 (Output max can be as high as 450 mV while input max can be no higher than 800mV). This limits the loading on the outputs.

Architecture of 8086:

Above Figure  shows the internal architecture of 8086. It is divided in mainly two groups named as Execution Unit(EU) & Bus Interface Unit(BIU). 

The EU contains Data registers, 16 bit ALU, PSW, Control Logic. The BIU contains Segment registers, Instruction queue, Stack Pointer Registers & Index Register.

           The control unit working registers are divided into three groups according to their functions. There are data group, which is set of arithmetic registers, the pointer group, which include base & index registers,  stack pointer & the segment group which is a set of special base registers. 

          The data group consists of the AX, BX, CX, DX registers. These registers are used to store operands & result of operations. AX, BX, CX, DX registers are  used as 16 bit registers but they can be also used as 8 bit registers as:

            AX:- AL & AH

            BX:- BL & BH

            CX:- CL & CH

            DX:- DL & DH

      The pointer & index group consists of IP, SP, BP, SI & DI registers. The IP(Instruction Pointer) & SP(Stack Pointer) registers are essentially the program counter & stack pointer but the complete instruction& addresses are formed by adding the contents of these registers to the contains of code segments(CS) & stack segments(SS).BP is base register for accessing the stack SI & DI registers for indexing. The segment group consists of Code, Data, Extra, Stack Segments.

Flag register of 8086:

         A flag is a flip-flop which indicates some conditions produced by the execution of an instruction or controls certain operations of EU. A 16 bit flag register in EU contains nine active flags. These flags are as follows.

U

U

U

U

OF

DF

IF

TF

SF

ZF

U

AF

U

PF

U

CF

   15      14      13      12       11     10      09      08      07      06       05     04       03      02     01       00    

The flag register has two categories in itself

1)      Conditional flags including carry flag(CF), parity flag(PF), auxiliary carry flag(AF), sign flag(SF), zero flag(ZF), overflow flag(OF).

2)      Control flags including direction flag(DF), interrupt flag(IF), trap flag(TF)

The description for the above flag register according to the numbers below is specified here.

i) Sign flag:- It indicates whether the result of operation is positive or negative.

ii) Zero flag:- It is set when the result of arithmetic operation is zero.

iii) Parity flag:- It is set when the low order 8 bit of the result contains an even number of 1’s.

iv) Carry flag:- It is set when the carry/borrow is generated after arithmetic operations.

v)  Auxillary Carry flag:- Set, if there is carry/borrow by bit 3 during addition/subtraction.

vi) Overflow flag:- It is set if there is a carry generated from D7 bit to D8 bit.

vii) Direction flag:- It is set if the direction of data accessing starts from higher address otherwise starts from lower address.

viii) Interrupt flag:- If interrupt is generated during the execution this flag is set.

ix) Trap flag:- If set then the NMI interrupt will be present otherwise if the NMI pin is high this condition is false.